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ds05-11240-1e fujitsu semiconductor data sheet memory 4 m 32 bit hyper page mode dram module MB8504E032AA-60/-70 4 m 32 bit hyper page mode dram module, 5 v, 1-bank n description the fujitsu mb8504e032aa is a fully decoded, cmos dynamic random access memory (dram) module consisting of eight mb8117405a devices. the mb8504e032aa is optimized for those applications requiring high speed, high performance and large memory storage. the operation and electrical characteristics of the mb8504e032aa are the same as the mb8117405a which features hyper page mode operation providing extended valid time for data output and higher speed random access of upto 2,048-bit of data within the same row than the fast page mode. for ease of memory expansion, the mb8504e032aa is offered in a 72-pad single in-line memory module package (simm). n product line & features parameter MB8504E032AA-60 mb8504e032aa-70 ras access time 60 ns max. 70 ns max. random cycle time 104 ns min. 124 ns min. address access time 30 ns max. 35 ns max. cas access time 15 ns max. 17 ns max. hyper page mode cycle time 25 ns min. 30 ns min. power dissipation operating mode 4620 mw max. 3960 mw max. standby mode 44 mw (cmos) / 88 mw (ttl) organization : 4,194,304 words 32 bits memory : mb8117405a, 8 pcs 5.0v 10% supply voltage 2,048 refresh cycles / 32.8 ms hyper page mode operation (edo) package and ordering information: 72-pin simm, order as mb8504e032aa-xxsg (sg = gold pad) mb8504e032aa-xxss (ss = gold pad)
2 MB8504E032AA-60/-70 n absolute maximum ratings (see warning) warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n package parameter symbol value unit supply voltage v cc ?.5 to +7.0 v input voltage v in ?.5 to +7.0 v output voltage v out ?.5 to +7.0 v short circuit output current i out 50 ma power dissipation p d 8w storage temperature t stg ?5 to +125 c -70 67 68 69 70 pin # symbol -60 pd1 pd2 pd3 pd4 v ss n.c. n.c. n.c. v ss n.c. v ss n.c. (mss-72p-p77) (mss-72p-p79) plastic simm package 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 dq0 dq1 dq2 dq3 v cc a0 a2 a4 a6 dq4 dq5 dq6 dq7 a7 v cc a9 ras 2 n.c. n.c. cas 0 cas 3 ras 0 n.c. n.c. dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 n.c. pd2 pd4 v ss v ss dq16 dq17 dq18 dq19 n.c. a1 a3 a5 a10 dq20 dq21 dq22 dq23 n.c. a8 n.c. n.c. n.c. v ss cas 2 cas 1 n.c. we dq8 dq9 dq10 dq11 dq12 v cc dq13 dq14 dq15 pd1 pd3 n.c.
3 MB8504E032AA-60/-70 functional block diagram w w w w w w w w oe oe ras cas ras cas oe ras cas oe ras cas oe ras cas oe ras cas oe ras 0 cas 0 cas 1 ras 2 cas 2 cas 3 we a0 to a10 v cc v ss i/o i/o i/o i/o a0 to a10 chip 00 ras cas c0 to 7 chips 00 to 07 chips 00 to 07 a0 to a10 chip 01 a0 to a10 chip 02 oe a0 to a10 chip 03 ras cas a0 to a10 chip 04 a0 to a10 chip 05 a0 to a10 chip 06 a0 to a10 chip 07 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31
4 MB8504E032AA-60/-70 n recommended operating condition (referenced to v ss ) * : undershoots of up to ?.0 volts with a pulse width not exceeding 10 ns are acceptable warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. parameter symbol min. typ. max. unit supply voltage v cc 4.5 5.0 5.5 v ground v ss ?v input high voltage, all inputs v ih 2.4 6.5 v input low voltage, all inputs* v il ?.3 0.8 v ambient temperature t a 070 c
5 MB8504E032AA-60/-70 n dc characteristics (at recommended operating conditions unless otherwise noted.) notes: *1. referenced to v ss . *2. i cc depends on the output load conditions and cycle rate. the speci? values are obtained with the output open. i cc depends on the number of address change as ras = v il and cas = v ih , v il > ?.3 v. i cc1 , i cc3 , i cc4 and i cc5 are speci?d at one time of address change during ras = v il and cas = v ih . i cc2 is speci?d during ras = v ih and v il > ?.3v. n capacitance (t a = 25 c, f = 1 mhz, v cc = 5.0 v) parameter notes symbol condition value unit min. max. output high voltage *1 v oh i oh = ?.0 ma 2.4 v output low voltage *1 v ol i ol = 4.2 ma 0.4 v input leakage current ras i i(l) 0 v v in v cc , 4.5 v v cc 5.5 v, v ss = 0 v, all other pins not under test = 0 v 30 m a cas 20 address, we 60 output leakage current i o(l) 0 v v out 5.5 v, data out disabled ?0 10 m a operating current (average power supply current) *2 MB8504E032AA-60 i cc1 ras & cas cycling, t rc = min ma mb8504e032aa-70 standby current (power supply current) ttl level i cc2 ras = cas = v ih ras = cas 3 v cc ?.2 v ma cmos level refresh current#1 (average power supply current) *2 MB8504E032AA-60 i cc3 cas = v ih , ras = cycling, t rc = min ma mb8504e032aa-70 hyper page mode current *2 MB8504E032AA-60 i cc4 ras = v il , cas = cycling, t hpc = min 720 ma mb8504e032aa-70 640 refresh current#2 (average power supply current) *2 MB8504E032AA-60 i cc5 ras cycling, cas -before-ras , t rc = min ma mb8504e032aa-70 parameter symbol typ. max. unit input capacitance, a0 to a10 c in1 ?1pf input capacitance, ras 0 and ras 2 c in2 ?9pf input capacitance, cas 0 to cas 3 c in3 ?3pf input capacitance, we c in4 ?6pf i/o capacitance, (dq0-31) c dq ?2pf ?0 ?0 ?0 840 720 16 8 840 720 840 720
6 MB8504E032AA-60/-70 n ac characteristics (at recommended operating conditions unless otherwise noted.) notes 1, 2, 3 (continued) no. parameter notes symbol MB8504E032AA-60 mb8504e032aa-70 unit min. max. min. max. 1 time between refresh t ref 32.8 32.8 ms 2 random read/write cycle time t rc 104 124 ns 3 access time from ras *4,7 t rac ?0?0ns 4 access time from cas *5,7 t cac ?5?7ns 5 column address access time *6,7 t aa ?0?5ns 6 output hold time t oh 3?ns 7 output hold time from cas t chc 5?ns 8 output buffer turn on delay time t on 0?ns 9 output buffer turn off delay time *8 t off ?5?7ns 10 output buffer turn off delay time from ras *8 t ofr ?5?7ns 11 output buffer turn off delay time from we *8 t wez ?5?7ns 12 transition time t t 150150ns 13 ras precharge time t rp 40?0ns 14 ras pulse width t ras 60 100000 70 100000 ns 15 ras hold time t rsh 15?7ns 16 cas to ras precharge time t crp 5?ns 17 cas to ras delay time *9.10 t rcd 14 45 14 53 ns 18 cas pulse width t cas 10?3ns 19 cas hold time t csh 40?0ns 20 cas precharge time (normal) *15 t cpn 10?0ns 21 row address set up time t asr 0?ns 22 row address hold time t rah 10?0ns 23 column address set up time t asc 0?ns 24 column address hold time t cah 10?0ns 25 column address hold time from ras t ar 24?4ns 26 ras to column address delay time *11 t rad 12 30 12 35 ns 27 column address to ras lead time t ral 30?5ns 28 column address to cas lead time t cal 23?8ns 29 read command set up time t rcs 0?ns 30 read command hold time referenced to ras *12 t rrh 0?ns 31 read command hold time referenced to cas *12 t rch 0?ns
7 MB8504E032AA-60/-70 (continued) no. parameter notes symbol MB8504E032AA-60 mb8504e032aa-70 unit min. max. min. max. 32 write command set up time *13 t wcs 0?ns 33 write command hold time t wch 10?0ns 34 write command hold time from ras t wcr 24?4ns 35 we pulse width t wp 10?0ns 36 write command to ras lead time t rwl 15?7ns 37 write command to cas lead time t cwl 10?3ns 38 din set up time t ds 0?ns 39 din hold time t dh 10?0ns 40 date hold time from ras t dhr 24?4ns 41 ras precharge time to cas active time (refresh cycles) t rpc 5?ns 42 cas set up time (c-b-r refresh) t csr 0?ns 43 cas hold time (c-b-r refresh) t chr 10?2ns 44 we set up time from ras *16 t wsr 0?ns 45 we hold time from ras *16 t whr 10?0ns 46 ras to data in delay time t rdd 15?7ns 47 cas to data in delay time t cdd 15?7ns 48 din to cas delay time t dzc 0?ns 49 we precharge time t wpz 8?ns 50 we to data in delay time t wed 15?7ns 51 hyper page mode ras pulse width t rasp 100000 100000 ns 52 hyper page mode read/write cycle time t hpc 25?0ns 53 access time from cas precharge *7,14 t cpa ?5?0ns 54 hyper page mode cas precharge time t cp 10?0ns 55 hyper page mode ras hold time from cas precharge t rhcp 35?0ns
8 MB8504E032AA-60/-70 notes: *1. an initial pause (ras = cas = v ih ) of 200 m s is required after power-up followed by any eight ras -only cycles before proper device operation is achieved. if an internal refresh counter is used, a minimum of eight cas - before-ras initialization cycles are required instead of eight ras cycles. *2. ac characteristics assume t t = 5 ns. *3. v ih (min) and v il (max) are reference levels for measureing the timing of input signals. transition times are measured between v ih (min) and v il (max). *4. assumes that t rcd t rcd (max), t rad t rad (max). if t rcd is greater than the maximum recommended value shown in this table, t rac will be increased by the amount that t rcd exceeds the value shown. *5. if t rcd 3 t rcd (max), t rad 3 t rad (max), and t asc 3 t aa - t cac - t t , access time is t cac . *6. if t rad 3 t rad (max) and t asc 3 t aa - t cac - t t , access time is t aa . *7. measured with a load equivalent to two ttl loads and 100 pf. *8. t off , t ofr and t wez are speci?d that output buffer change to high impedance state. *9. operation within the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is speci?d as a reference point only; if t rcd is greater than the speci?d t rcd (max) limit, access time is controlled exclusively by t cac or t aa . *10. t rcd (min) = t rah (min)+ 2 t t + t asc (min). *11. operation within the t rad (max) limit ensures that t rac (max) can be met. t rad (max) is speci?d as a reference point only; if t rad is greater than the speci?d t rad (max) limit, access time is controlled exclusively by t cac or t aa . *12. either t rrh or t rch must be satis?d for a read cycle. *13. t wcs is speci?d as a reference point only. if t wcs 3 t wcs (min) the data output pin will remain high-z state through entire cycle. *14. t cpa is access time from the selection of a new column address (caused by changing cas from ? to ??. therefore, if t cp become long, t cpa also become longer than t cpa (max). *15. assumes that cas -before-ras refresh. *16. assumes that test mode function. *source: see mb8117405a data sheet for details on the electricals.
9 MB8504E032AA-60/-70 n package dimensions 72-pad plastic single in-line type module (case no.: mss-72p-p77) +0.10 C0.08 +.004 C.003 * resistor mounting area. (.995.005) 25.270.13 (4.250.005) (3.984.004) details of "a" part 2.54(.100)min 0.25(.010)max 1.04(.041)typ "a" 5.08(.200)max 5.72(.225)min 1.27 .050 pin no.1 index (3.750.002) 95.250.05 (.050.001) 1.270.03 (.250.005) 6.350.13 1 (.400.003) 10.160.08 (1.750.002) 44.450.05 (.250.001) 6.350.03 (r.062.002) r1.570.05 (.080.005) 2.030.13 (.250.005) 6.350.13 (?.125.002) ?3.180.05 (r.062.002) r1.570.05 107.950.13 101.190.10 1995 fujitsu limited m72078sc-1-1 c dimension in mm (inches)
10 MB8504E032AA-60/-70 72-pad plastic single in-line type module (case no.: mss-72p-p79) +0.15 C0.08 +.006 C.003 * resistor mounting area. (.995.005) 25.270.13 (4.250.005) (3.984.004) details of "a" part 2.54(.100)min 0.25(.010)max 1.04(.041)typ "a" 5.08(.200)max 5.72(.225)min 1.27 .050 pin no.1 index (3.750.002) 95.250.05 (.050.001) 1.270.03 (.250.005) 6.350.13 1 (.400.003) 10.160.08 (1.750.002) 44.450.05 (.250.001) 6.350.03 (r.062.002) r1.570.05 (.080.005) 2.030.13 (.250.005) 6.350.13 (?.125.002) ?3.180.05 (r.062.002) r1.570.05 107.950.13 101.190.10 1995 fujitsu limited m72080sc-1-1 c dimension in mm (inches)
11 MB8504E032AA-60/-70 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9704 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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